1. Field of the Invention
The present invention relates to a test device, and in particular to a test device for detecting alignment of bit lines and bit line contacts in DRAM devices, as well as a test method thereof.
2. Description of the Related Art
FIG. 1a is a layout of conventional deep trench capacitors in a memory device. Deep trench capacitors 10 are disposed under the passing word lines. Transistors 14 are electrically coupled to the storage nodes 16 of the capacitors 10 through the diffusion regions 18. The diffusion regions 20 are connected to plugs 22 coupled to bit lines (not shown). The transistors 14 are driven by word lines 12, and the channels under the word lines 12 are conductive when appropriate voltages are applied to the word lines 12. Consequently, the current produced between the diffusion regions 18 and 20 may flow into or out of the storage nodes 16.
FIG. 1b is a cross-section of FIG. 1a. After the deep trench capacitors 10 are completely formed in the substrate, trench isolations are formed in the substrate and deep trench capacitors 10 to define active areas. The word lines 12 are then formed on the substrate, the diffusion regions 18 and 20 are formed in the active areas by word lines 12 during the implant process, and the diffusion regions 18 and 20 are located on both sides of the word lines 12. Finally, the plugs 22 are formed on the diffusions 20. The adjacent memory cells may experience current leakage and cell failure, reducing process yield, if bit line masks and contacts are not aligned accurately.
Therefore, the process yield and reliability of the memory cells can be improved if alignment inaccuracy between the masks of active areas and the deep trench capacitors is controlled within an acceptable range.
Accordingly, an object of the invention is to detect alignment of bit lines and bit line contacts in DRAM devices.
According to the above mentioned objects, the present invention provides a test device for detecting alignment of bit lines and bit line contacts in DRAM devices.
In the test device of the present invention, an active area is disposed in the scribe line area. Parallel first and second bar-type bit line contacts are disposed in the active area. The first and second bar-type bit line contacts are shorter than the active area, and each bar-type line contact has an outside surface and two terminals. First and second bit lines are disposed in the active area, the first bar-type bit line contact is covered by the first bit line with a first outside surface aligned with the outside surface of the first bar-type contact. The second bar-type bit line contact is covered by the second bit line with a second outside surface aligned with the outside surface of the second bar-type contact. First and second plugs are disposed on the two terminals of the first bit line respectively. Third and fourth plugs are disposed on the two terminals of the second bit line respectively.
According to the above mentioned objects, the present invention also provides a method for detecting alignment of bit lines and bit line contacts in DRAM devices.
In the method of the present invention, a wafer with at least one scribe line region and at least one memory region is provided. A plurality of memory cells in the memory region and at least one test device in the scribe line region are formed simultaneously, wherein the memory region has bit line contacts and bit lines. A first resistance is detected by the first plug and the second plug, and the second resistance is detected by the third plug and the fourth plug, respectively. Alignment of the bar-type bit line contacts and the bit lines of the test device is determined according to the first resistance and the second resistance. Finally, alignment of the bit line contacts and the bit lines is determined according to alignment of the bar-type bit line contacts and bit lines of the test device.